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Put two chips, runtimes, or runtime versions side by side. Everything else is held fixed or called out, so a ratio is worth exactly what the matched runs say.
Ratios read side A relative to side B. Geometric mean over 2 like-for-like pairs.
Everything else matches: model, quantisation, backend, protocol, and workload are the same on both sides.
Each row is a configuration present on both sides. Values are per-cell medians; ratios read Apple M1 Max relative to Apple M3 Ultra.
| Configuration | Decode A | Decode B | Ratio | Prefill A | Prefill B | Ratio | Runs A / B |
|---|---|---|---|---|---|---|---|
Qwen3.5-2B BaseRTQ4 | 188.8 | 309.0 | 0.61× | 1,263 | 3,621 | 0.35× | 2 / 2 |
Qwen3.5-2B BaseRTQ8 | 140.3 | 227.7 | 0.62× | 1,235 | 3,586 | 0.34× | 2 / 2 |
Top 4 of 4 runs by decode throughput.
| Model / format | Chip / backend | Decode | Prefill | Contributor | Date | Report |
|---|---|---|---|---|---|---|
Qwen3.5-2B-Q4 BaseRT 0.2.6Q4 | Apple M1 Max Metal | 192.9 TG128 @ 1 ctx | 429 PP512 | basecompute | View Benchmark | |
Qwen3.5-2B-Q4 BaseRT 0.3.0Q4 | Apple M1 Max Metal | 184.7 TG128 @ 1 ctx | 2,096 PP512 | basecompute | View Benchmark | |
Qwen3.5-2B-Q8 BaseRT 0.2.6Q8 | Apple M1 Max Metal | 141.5 TG128 @ 1 ctx | 400 PP512 | basecompute | View Benchmark | |
Qwen3.5-2B-Q8 BaseRT 0.3.0Q8 | Apple M1 Max Metal | 139.1 TG128 @ 1 ctx | 2,070 PP512 | basecompute | View Benchmark |
Top 4 of 4 runs by decode throughput.
| Model / format | Chip / backend | Decode | Prefill | Contributor | Date | Report |
|---|---|---|---|---|---|---|
Qwen3.5-2B-Q4 BaseRT 0.3.0Q4 | Apple M3 Ultra Metal | 311.3 TG128 @ 1 ctx | 5,484 PP512 | basecompute | View Benchmark | |
Qwen3.5-2B-Q4 BaseRT 0.2.6Q4 | Apple M3 Ultra Metal | 306.7 TG128 @ 1 ctx | 1,759 PP512 | basecompute | View Benchmark | |
Qwen3.5-2B-Q8 BaseRT 0.3.0Q8 | Apple M3 Ultra Metal | 232.5 TG128 @ 1 ctx | 5,415 PP512 | basecompute | View Benchmark | |
Qwen3.5-2B-Q8 BaseRT 0.2.6Q8 | Apple M3 Ultra Metal | 222.9 TG128 @ 1 ctx | 1,756 PP512 | basecompute | View Benchmark |