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Put two chips, runtimes, or runtime versions side by side. Everything else is held fixed or called out, so a ratio is worth exactly what the matched runs say.

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Runs compared: 6
Like-for-like pairs: 2
Chips available: 6

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Side A

Side B

Model

Runtime

Runtime version

Quantisation

Backend

Prefill size

Decode size

Cooldown

4 runs vs 2 runs · 2 like-for-like pairs

Held fixedModel: Qwen3 4BPrefill: PP512Decode: TG128

Apple M1 Max has only 2 matching runs. Treat its figures as indicative.
A side mixes quantisations. Pick a quantisation to compare the same weights.
The sides differ in cooldown, conditioning, decode workload, harness schema. Ratios may reflect benchmark protocol rather than the chip.

Chip comparison

Apple M5 Pro vs Apple M1 Max

Ratios read side A relative to side B. Geometric mean over 2 like-for-like pairs.

Decode: 0.97×-3.1%
Prefill: 3.68×+268%

Side A

Apple M5 Pro

4 runs

2 contributors

Latest 11 Sep 2026

Decode · TG128: 98.7tok/s median
best 107.3 · worst 64.7
Prefill · PP512: 3,378tok/s median
best 3,412 · worst 2,705

Models: Qwen3-4B
Runtimes: BaseRTllama.cpp
Versions: BaseRT 0.2.4, llama.cpp b9960 (a935fbffe)
Quantisations: Q4, Q4_0, Q8
Backends: BLAS + Metal, Metal
Cooldown: off, on
Conditioning: idle_reset_then_warm, runtime_native_warmup, warmup_only
Decode workload: TG128
Harness schema: basert-benchmark-harness/1, computearena-measurements/1

Side B

Apple M1 Max

2 runs

1 contributor

Latest 20 Sep 2026

Decode · TG128: 86.6tok/s median
best 101.9 · worst 71.3
Prefill · PP512: 924tok/s median
best 927 · worst 920

Models: Qwen3-4B-Q4, Qwen3-4B-Q8
Runtimes: BaseRT
Versions: BaseRT 0.2.6
Quantisations: Q4, Q8
Backends: Metal
Cooldown: off
Conditioning: warmup_only
Decode workload: TG128 @ 1 ctx
Harness schema: basert-benchmark-harness/1

What differs besides the chip

Facet	Apple M5 Pro	Apple M1 Max
Model	Qwen3-4B	Qwen3-4B-Q4, Qwen3-4B-Q8
Runtime	BaseRT, llama.cpp	BaseRT
Runtime version	BaseRT 0.2.4, llama.cpp b9960 (a935fbffe)	BaseRT 0.2.6
Quantisation	Q4, Q4_0, Q8	Q4, Q8
Backend	BLAS + Metal, Metal	Metal
Cooldown	off, on	off
Conditioning	idle_reset_then_warm, runtime_native_warmup, warmup_only	warmup_only
Decode workload	TG128	TG128 @ 1 ctx
Harness schema	basert-benchmark-harness/1, computearena-measurements/1	basert-benchmark-harness/1

Like-for-like pairs

Each row is a configuration present on both sides. Values are per-cell medians; ratios read Apple M5 Pro relative to Apple M1 Max.

Configuration	Decode A	Decode B	Ratio	Prefill A	Prefill B	Ratio	Runs A / B
Qwen3-4B BaseRTQ4	105.6	101.9	1.04×	3,378	927	3.64×	2 / 1
Qwen3-4B BaseRTQ8	64.7	71.3	0.91×	3,412	920	3.71×	1 / 1

Side A · Apple M5 Pro

Top 4 of 4 runs by decode throughput.

Model / format	Chip / backend	Decode	Prefill	Contributor	Date	Report
basecompute/Qwen3-4B BaseRT 0.2.4Q4	Apple M5 Pro Metal	107.3 TG128	3,384 PP512	arki05	10 Sep 2026	View Benchmark
basecompute/Qwen3-4B BaseRT 0.2.4Q4	Apple M5 Pro Metal	103.9 TG128	3,372 PP512	arki05	10 Sep 2026	View Benchmark
Qwen3-4B llama.cpp b9960 (a935fbffe)Q4_0	Apple M5 Pro BLAS + Metal	93.6 TG128	2,705 PP512	isu	10 Sep 2026	View Benchmark
basecompute/Qwen3-4B BaseRT 0.2.4Q8	Apple M5 Pro Metal	64.7 TG128	3,412 PP512	arki05	11 Sep 2026	View Benchmark

Side B · Apple M1 Max

Top 2 of 2 runs by decode throughput.

Model / format	Chip / backend	Decode	Prefill	Contributor	Date	Report
Qwen3-4B-Q4 BaseRT 0.2.6Q4	Apple M1 Max Metal	101.9 TG128 @ 1 ctx	927 PP512	basecompute	20 Sep 2026	View Benchmark
Qwen3-4B-Q8 BaseRT 0.2.6Q8	Apple M1 Max Metal	71.3 TG128 @ 1 ctx	920 PP512	basecompute	20 Sep 2026	View Benchmark